VHDL de yeniyim ve bi çok bilmediğim var ve hocam pek yardımcı olmuyor. kaynak vrsa bildiğiniz paylaşır mısnız?
çükü bir tutorial yapıp proje verdi ve projemde RAM üzerine. bende araştırdım ve static ram için yazılmışını buldum. Ancak portlarda ki giriş ve çıkışları anlamadım.
VHDL CODE for the SRAM
--------------------------------------------------------------
-- 4*4 RAM module
--
-- KEYWORD: array, concurrent processes, generic, conv_integer
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------
entity SRAM is
generic( width: integer:=4;
depth: integer:=4;
addr: integer:=2);
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in std_logic_vector(addr-1 downto 0);
Write_Addr: in std_logic_vector(addr-1 downto 0);
Data_in: in std_logic_vector(width-1 downto 0);
Data_out: out std_logic_vector(width-1 downto 0)
);
end SRAM;
--------------------------------------------------------------
architecture behav of SRAM is
-- use array to define the bunch of internal temparary signals
type ram_type is array (0 to depth-1) of
std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
-- Read Functional Section
process(Clock, Read)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
-- Write Functional Section
process(Clock, Write)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;
----------------------------------------------------------------
Test bench for the SRAM
--------------------------------------------------------------------
-- Test Bench for memory module
--
-- use loop statement to test module completely
--------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity MEM_TB is -- entity declaration
end MEM_TB;
--------------------------------------------------------------------
architecture TB of MEM_TB is
component SRAM is
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in std_logic_vector(1 downto 0); -- Neden vector?
Write_Addr: in std_logic_vector(1 downto 0); -- Neye gore port ısımlerı verıyoruz
Data_in: in std_logic_vector(3 downto 0);
Data_out: out std_logic_vector(3 downto 0)
);
end component;
signal T_Clock, T_Enable, T_Read, T_Write: std_logic;
signal T_Data_in, T_Data_out: std_logic_vector(3 downto 0);
signal T_Read_Addr: std_logic_vector(1 downto 0);
signal T_Write_Addr: std_logic_vector(1 downto 0);
begin
U_CKT: SRAM port map (T_Clock, T_Enable, T_Read, T_Write,
T_Read_Addr, T_Write_Addr, T_Data_in, T_Data_out);
Clk_sig: process
begin
T_Clock<='1'; -- clock cycle 10 ns
wait for 5 ns;
T_Clock<='0';
wait for 5 ns;
end process;
process
variable err_cnt: integer := 0;
begin
T_Enable <= '1';
T_Read <= '0';
T_Write <= '0';
T_Write_Addr <= (T_Write_Addr'range => '0');
T_Read_Addr <= (T_Read_Addr'range => '0');
T_Data_in <= (T_Data_in'range => '0');
wait for 20 ns;
-- test write
for i in 0 to 3 loop
T_Write_Addr <= T_Write_Addr + '1';
T_Data_in <= T_Data_in + "10";
T_Write <= '1';
wait for 10 ns;
assert (T_Data_out="ZZZZ")
report "Something wrong!" severity Error;
if (T_Data_out /= "ZZZZ") then
err_cnt := err_cnt + 1;
end if;
end loop;
-- test read
for i in 0 to 2 loop
T_Read_Addr <= T_Read_Addr + '1';
T_Read <= '1';
wait for 10 ns;
assert (conv_integer(T_Data_out)=2*conv_integer(T_Read_Addr))
report "Something wrong!" severity Error;
if (conv_integer(T_Data_out)/=2*conv_integer(T_Read_Addr)) then
err_cnt := err_cnt + 1;
end if;
end loop;
-- summary of all the tests
if (err_cnt=0) then
assert false
report "Testbench of ROM completed successfully!"
severity note;
else
assert true
report "Something wrong, try again"
severity error;
end if;
wait;
end process;
end TB;
--------------------------------------------------------------------------
configuration CFG_TB of MEM_TB is
for TB
end for;
end CFG_TB;
--------------------------------------------------------------------------
xilinx in kendi template'inde ram için ornek vermiş ama çözemedim onuda =)
Merhaba,
Bu kitap direkt uygulamalı ve anlaşılır bir dilde yazılmış. Fikrim olsun diye okumuştum ama çalışabileceğim ortamım olmadığından sadece genel fikir edinmemi sağlamıştı. İnternette malum sitelerden bulabilirsiniz zira ucuz değil. Amazondaki yorumlar da iyi kitap olduğu yönünde.
http://www.amazon.com/FPGA-Prototyping-VHDL-Examples-Spartan-3/dp/0470185317/ref=sr_1_3?ie=UTF8&qid=1343298493&sr=8-3&keywords=vhdl